An MRAM cell basically includes a stacked structure of magnetic layers that are separated by a non-magnetic tunneling barrier layer to form a magnetoresistive tunnel junction (MTJ) element, or are separated by a conductive layer to form a magnetoresistive conductive junction (MCJ) element, both of which are commonly referred to as magnetoresistive junction elements. In MRAM cells, magnetization of one magnetic layer is fixed, while magnetization of another magnetic layer is free to be switched between two preferred directions along an easy axis thereof. One bit of logic information can thus be stored by selecting the orientation of the freely switchable magnetization with respect to the fixed magnetization.
Standard CMOS processing for manufacturing of MRAMs starts with preparing a silicon or other suitable semiconductor substrate that is provided with active structures such as transistors and the like. Above the semiconductor substrate, metal lines and via contacts are formed to provide interconnections for the integrated circuit and the magnetoresistive memory cell array. These interconnections typically are formed by the well-known damascene technique which starts with depositing a dielectric layer on the semiconductor substrate, followed by masking and etching thereof, and depositing metallic material which is planarized to create embedded metallic structures that can be accessed from above.
In accordance with the standard CMOS process nomenclature, metallic lines forming the first layer of interconnects are referred to as the first metallization layer (M1). Via contacts formed in a layer of dielectric material deposited on M1 are referred to as the first via layer (V1). Metal lines formed in a layer of dielectric material deposited on V1 are referred to as the second metallization layer (M2), followed in sequence by a second via layer (V2) formed thereupon, and so on, to provide as many via layers and metallization layers as are needed for the specific apparatus and application.
Reference is now made to FIGS. 1A through 1D depicting vertical sectional views of intermediate products in a standard CMOS process of manufacturing MRAM cells. Accordingly, starting with the arrangement shown in FIG. 1A, a layer of dielectric material that is not further detailed in the figures is formed on a semiconductor substrate (not shown) and is provided with metallic lines 1, e.g., made of copper (Cu), to thereby create a metallization layer, which can be identified as M2. Thereupon, a dielectric bilayer 2 which, for example, can be made of silicon nitride (SiN) or silicon carbide (SiC) is formed, through which via 3 is formed to create a via layer, which can be identified as V1. Via 3 conductively connects metal line 1′ with conductive plate 4 formed on V1. Conductive plate 4 is in electric contact with a magnetoresistive junction element 5 formed on conductive plate 4. On the magnetoresistive junction element 5 in electric contact therewith, a hard mask 6 made of metallic material is formed to have a thickness B of, for example, more than 140 nanometers (nm), followed by embedding magnetoresistive junction element 5 and hard mask 6 in a dielectric layer 7 made of, for example, silicon oxide, onto which, typically, a SiN-layer 8 is formed to thereby enhance deposition of a thick interlayer dielectric (ILD) 9, for example made of silicon oxide. Thick ILD 9 then is planarized, for example, using chemical-mechanical polishing (CMP), to reduce ILD 9, for example, to a layer thickness A of about 660 nm (see FIG. 1B).
After thinning ILD 9, first trench 10 above magnetoresistive junction element 5 uncovering the hard mask 6 and second trench 11 above the conductive line 1″ are formed using conventional etch-lithography techniques. After deepening the second opening 11 to uncover the conductive line 1″, conductive material 12, 13 for electrically contacting the magnetoresistive junction element 5 via metallic hard mask 5 from above and for electrically contacting conductive line 1″ from above, respectively, is deposited (see FIGS. 1C and 1D). Accordingly, depositing conductive materials 12, 13 results in creating dual via contacts for electrically connecting magnetoresistive junction element 5 and conductive line 1″ to metallic lines formed thereupon.
Etching of the first and second trenches 10, 11 is typically a two-step process, i.e., a first etch step of simultaneously etching first trench 10 down to hard mask 6 and second trench 11 down to the height of protrusion 20, followed by a second etch step to etch second trench 11 down to conductive line 1″.
In conventional manufacturing of MRAM cells as explained with reference to FIGS. 1A-1D, a direct interconnection between thick hard mask 6 and an upper conductive line is established to avoid inter-level shorts.
Inter-level shorts and opens typically behave like a pair of scales in M3 etch. If the M3 etch level is deeper, the yield of shorts decreases while the yield of opens increases. Conversely, if the etch level is shallower, the inter-level short yield improves in inverse proportion to the open yield's decrease. As inter-level short and open yield has been very sensitive to this trench etch amount, the M3 etch needs a very powerful endpoint system and process window. However, the M3 etch process window depends mainly on the MTJ hardmask thickness in conventional integration, which is the physical length from the upper conductive line to the MB plate.
Basically, this kind of poor processing window results from poor integration, which does not have any stopping layer though the trench pattern is designed with several different pattern densities, called the pattern loading effect.
Other effects that diminish the process margin include dielectric deposition and CMP non-uniformity as well as etch non-uniformity. However, these non-uniformities have an effect on the worse process window in the conventional structure, because non-uniformity and the pattern loading effect can be absorbed by a stop layer with a highly selective etch process.